The Model 7166/H QDC implements 16 channels of Charge to Digital Conversion (QDC) followed by a digital processing section and CAMAC interface in a single width CAMAC module. To minimize data readout time, the QDC performs a sparse data function. Channels can be individually programmed with pedestal correction and both lower and upper level thresholds. Digitization starts following release of the common GATE input. It may be delayed by a user-programmable amount to allow time for derivation of fast CLEAR signals.
Channels that meet the sparsification requirements will have corresponding bits set in the Hit Register. Subsequent events will be ignored until the Hit Register is cleared either by completing a sparse read of the module or via front panel fast CLEAR or CAMAC Clear commands.
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