The Model 7164 PEAK ADC implements 16 channels of Peak Detect and Hold followed by a digital processing section and CAMAC interface in a single width CAMAC module. To minimize data readout time, the ADC performs a sparse data function. Channels can be individually programmed with pedestal correction and both lower and upper level thresholds. Digitization starts following release of the Common GATE input. It may be delayed by a user-programmable amount to allow time for derivation of fast CLEAR signals before digitization starts.
Channels that meet the sparsification requirements will have corresponding bits set in the Hit Register. Subsequent events will be ignored until the Hit Register is cleared either by completing a sparse read of the module or via front panel fast CLEAR or CAMAC Clear commands.
Unless otherwise noted, specifications are for single-ended 4.096 Volts full scale and 50 ohm input impedance. Consult factory for available optional ranges up to ±10V full scale and input impedance up to 1K ohm.
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