How can I use the Hit Register and Sparsification?

The Hit Register shows which channels have data.  Separate pedestals, upper and lower thresholds may be set for each channel.  They are enabled using bits in the Control Register.  Pedestals in 2's complement are added to the data before threshold comparisons.  Bits in the Hit Register are set during digitization for those channels whose pedestal corrected data falls within their upper and lower thresholds. (If thresholds are not enabled, all channels are considered to have valid data and all channels will set their bits in the Hit Register during digitization)
Sparse Data Reads return only those channels with their bits set in the hit register, starting with the highest numbered channel.  Valid data returns Q=1.  As channels are read, their Hit Register bits are reset.  When the final channel has been read, LAM is reset, Hit Register is down to Zero allowing the front end to take data again.  The following Sparse Data Read returns Q=0.

Sample Sparse Read Procedure  
Set thresholds and pedestals using the F(17) and F(20) commands as required before taking data.
Enables LAM
F(11) A(3)
Clears the Hit Register, Data Memory and Resets the LAM
External Gated Event
External Test Event
*   F(8) Loop
Test LAM looking for Q=1
** F(4) Loop
Read Highest to Lowest Channel whose Data Bits are set in the Hit Register until Q=0
 Go to 3rd step  (External Gated Event) and repeat the procedure.

* An F(8) Loop  to Test the LAM  by continuously polling the module and looking for Q=1.  The module will not accept this command until the conversion cycle has completed. therefore the Q should = 0 until the module is ready to be read.
** An F(4) Loop should Read until Q=0 which indicates the buffer is empty. (While Q=1 the data is valid)

Example: Remember - the data word has the Channel Number in the upper 4 bits of the 16 bit word.
Lets say after the event, three channels have data (Channels 1, 3 and 5).  If you read the Hit Register, you would read 21 (Channel 1 sets the 1 bit, Channel 3 sets the 4 bit and Channel 5 sets the 16 bit).  The first F(4) would read the data from channel 5 (the highest channel with its bit set in the hit register) and Q=1.  This is valid data.  If you read the Hit Register now, you would read 5 (Channel 5's bit is reset during that read).  The next F(4) would read channel 3's data with Q=1 and reset it's bit in the Hit Register.  Now if you read the Hit register, it would read 1.  The next F(4) will read Channel 1's data with Q=1.  NOW the Hit Register is empty, the LAM is reset, and the front end is enabled to accept data again. The following F(4) will re-read the last data word in the buffer but Q=0 so you will know the data is not valid and you can ignore it.  With this method, you will need to execute one more F(4) Sparse Read then the number of Channels with valid data.

Another method is to read the Hit Register first [F(6) A(1)] and knowing how many channels have data, you can set up your loop for that many F(4) read cycles.  In the above example, the Hit register reads 21 (0000 0000 0001 0101 in binary) which tells you 3 channels have data (Channel 1, Channel 3, and Channel 5).

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