What is meant by Conversion Time? Is it for each channel or is it for all 16 channels?

Conversion Time for each of the modules is 7.2us, which includes converting all 16 Channels

7164, 7166,7167, and 7187 - A Gate Signal is applied to the front panel which enables all channels to accept data. Each channel has a "Sample/Hold" circuit. During the Gated time, the module is in "Sample" mode. (The Start pulse in the 7187 begins the "Sample" mode). Once the Gate Signal turns off, the channels go into "Hold" mode (The Stop pulse in the 7187 switches to "Hold" mode.) locking out the front end and keeping the module from accepting any more data until cleared. The CONVERSION TIME is the time it takes to multiplex the data from all 16 "Sample/Hold" circuits through the ADC and into memory  It is 7.2us and timing begins at the back edge of the GATE pulse.

7186 - The Start pulse begins "Sample" mode and the Stop pulse switches to "Hold" mode. This module uses timing from the COMMON signal to start the Conversion Cycle. In COMMON START mode, some ranges require additional conversion delay as described below*.  The  CONVERSION TIME is 7.2us and the timing begins at the leading edge of the COMMON pulse, although the actual conversion begin 750ns later.

In ALL these modules, digitization may be delayed by an amount from 0 to 16us in 62.5ns increments using the jumpers at the rear of the module. This will allow a greater acceptance window for CLEAR signals if needed. Once digitization begins, you will not be able to clear or access the module until the conversion cycle has completed.

Conversion Time for each Module is 7.2us, which includes all 16 Channels

The timing starts at either the leading or trailing edge as shown in the following chart. The 7.2us Conversion Time includes the 600ns or 750ns delay mentioned below.

ADC 7164
Conversion starts 600ns after the trailing edge of the Gate signal.
QDC 7166, 7167
Conversion starts 750ns after the trailing edge of the Gate signal
TDC 7186, 7187
Conversion starts 750ns after the leading edge of the COMMON pulse
for the 7186, and 750ns after the trailing edge of the Gate pulse for the 7187

The 600ns and 750ns delay before starting the Conversions is for settling time and also allows time to accept fast clear signals.


It is recommended to delay digitization for the 7186 TDC when using COMMON START mode greater than 100ns full scale. This prevents the module from beginning the Conversion cycle to soon and still allows settling time and a few hundred nanoseconds acceptance window.
Example: If the module is set for 2us Full Scale with no additional delay, after 750ns from the Common Pulse (START), digitization begins. The module switches to "Hold" mode before Full Scale is reached therefore the highest reading you could get is around 750ns instead of 2us, This would also happen in channels with no stop pulses. The Manual shows the minimum recommended delays for the various Full Scale ranges when used in COMMON START mode. The chart is repeated here.  Note: The COMMON STOP mode does not require this.

100 nsec
200 nsec
125 nsec
400 nsec
312.5 nsec
800 nsec
750 nsec
1 usec
937.5 nsec
2 usec
1937.5 nsec
4 usec
3937.5 nsec
8 usec
7937.5 nsec
Other ranges
> (Range - 100 nsec)

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