I just received my new TDC, QDC or ADC .  Can you help me get started programming it?

One way to start , is to check the back end digital section first.  Then, the internal dataway logic.  And finally check the  ADC  and the front end using the internal tests for the module.  Once that is working correctly, you can attempt to take external data. One thing to remember is once an event occurs,  the front end is locked-out until the hit register is cleared.  Once it is cleared,  another event can be accepted.

Sample Memory Test:
Z
Always give a software Z (Initialize) on power-up.
F(16) A(0) D(X)
Write to channel 1 any data word between 0 through 4095
F(16) A(1) D(X)
Write to channel 2 another word
F(16) A(3) D(X)
Write to channel 3 another word
.Repeat for all Channels
Write Channels 4 through 16 as above
F(0) A(0)
Read Channel 1 Data  S/B the same as written   (Remember upper 4 bits read Channel #)
F(0) A(1)
Read Channel 2 Data
.F(0) A(2)
Read Channel 3 Data
Repeat for all Channels
Read Channels 4 through 16 as above


Back End Logic Test:  (Generates Data from just after the ADC Stage)
Z
Always give a software Z (Initialize) on power-up.
F(9)
Clear Module
F(17) A(4)
Select Test Register for next F(20) Command
F(20) A(0)
Put  "001001001001" Pattern in Test Register   ( 249 Hex )
F(25) A(0)
Generate digital test using pattern in test register for all Channels
DELAY
Wait at least 7.2us for module to multiplex data into memory. (Part of Conversion Cycle)
F(0) A(0)
Read Channel 1 Data  S/B the same as written   (Remember upper 4 bits read Channel #)
F(0) A(1)
Read Channel 2 Data
Repeat for all Channels
Read Channels 3 through 16 as above
You can repeat above test with different test patterns F(20) A(1),  F(20) A(2),  F(20) A(3).


Front End Test *:  (Generates Input Data from the Input stage of the Module)
Z
Always give a software Z (Initialize) on power-up.
F(9)
Clear Module
F(25) A (1)
Generates Front End Test (charge, voltage or time), see data sheet for individual modules
DELAY
Wait at least 7.2us before reading module  (7.2us  Conversion Cycle for all channels)
F(0) A(0)
Read Channel 1 Data    (should read data to tell module is functioning properly)
F(0) A(1) Read Channel 2 Data 
Repeat for all Channels Read Channels 3 through 16 as above
F(11) A(3)
Clear  Hit Register so module will be able to accept another event
F(25) A(2)
Generates Front End test using about double the data (charge, voltage or time) for all Channels.   See data sheet for individual modules
DELAY
Wait at least 7.2us before reading module  (7.2us  Conversion Cycle for all channels)
F(0) A(0)
Read Channel 1 Data    (should read greater than the data read from F(25) A(1) test)
F(0) A(1) Read Channel 2 Data 
Repeat for all Channels
Read Channels 3 through 16 as above
 * The above test is not for calibration.  It just shows whether the front end is operating properly.  See the Data Sheet for the specific module being tested (QDC, ADC, TDC) to approximate what the reading should be.

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